Testing of integrated circuits is an important part of the integrated circuit manufacturing process. Testing is used not only for preventing defective or unreliable chips from being shipped to customers, but also allows analysis of the fails so as to make adjustments to the design or fabrication steps of the chip. Conventional testing methodologies are based on models at the logic-level (gate-level) of the circuit design, which may not incorporate information about the physical implementation of the design. Tests generated from models may not completely test the circuit, and thus many physical defects may not be found or the failures they cause may be difficult to analyze and diagnose. Therefore, there exists a need for a method of generating test patterns and evaluating the test patterns based on how well the test patterns test the physical features and attributes associated with the features of an integrated circuit.
Further, prior art in this domain has focused on defect modeling techniques and testing for physical defects based on the aforementioned defect models. Defect models are not comprehensive and are often times based on one or a set of defect assumptions. Accordingly, there exists a need in the art to evaluate existing test patterns and generate test patterns to test for selected physical layout features.